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PRELIMINARY
CY2XF33
High Performance LVDS Oscillator with Frequency Margining - Pin Control
Features

Functional Description
The CY2XF33 is a high performance and high frequency Crystal Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed through two select pins, allowing easy frequency margin testing in applications. The CY2XF33 is available as a factory configured device or as a field programmable device.
Low Jitter Crystal Oscillator (XO) Less than 1 ps Typical RMS Phase Jitter Differential LVDS Output Output Frequency from 50 MHz to 690 MHz Two Frequency Margining Control Pins (FS0, FS1) Factory Configured or Field Programmable Integrated Phase-Locked Loop (PLL) Supply Voltage: 3.3V or 2.5V Pb-Free Package: 5.0 x 3.2 mm LCC Commercial and Industrial Temperature Ranges
Logic Block Diagram
4 C RYSTAL OSCILLATOR LOW -NOISE PLL OUTPUT DIVIDER 5 FS0 1
FREQUENCY SELECT DECODE
CLK
CLK#
FS1
2
Pinouts
Figure 1. Pin Diagram - 6 Pin Ceramic LCC
FS0 1 FS1 2 VSS 3
6 VDD 5 CLK# 4 CLK
Table 1. Pin Definitions - 6 Pin Ceramic LCC Pin 1, 2 4, 5 6 3 Name FS0, FS1 CLK, CLK# VDD VSS I/O Type CMOS Input LVDS Output Power Power Frequency Select Differential Output Clock Supply Voltage: 2.5V or 3.3V Ground Description
Cypress Semiconductor Corporation Document Number: 001-53148 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 18, 2009
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PRELIMINARY
CY2XF33
Functional Description
The FS0 and FS1 pins select between four different output frequencies, as shown in Table 2. Frequency margining is a common application for this feature. One frequency is used for the standard operating mode of the device, while the other frequencies are available for margin testing, either during product development or in system manufacturing test. Table 2. Frequency Select FS1 0 0 1 1 FS0 0 1 0 1 Output Frequency Frequency 0 Frequency 1 Frequency 2 Frequency 3
Programming Variables
Output Frequencies
The CY2XF33 is programmed with up to four independent output frequencies, which are then selected using the FS0 and FS1 pins. The device can synthesize frequencies to a resolution of 1 part per million (ppm), but the actual accuracy of the output frequency is limited by the accuracy of the integrated reference crystal. The CY2XF33 has an output frequency range of 50 MHz to 690 MHz, but the range is not continuous. The CY2XF33 cannot generate frequencies in the ranges of 521 MHz to 529 MHz and 596 MHz to 617 MHz.
Industrial Versus Commercial Device Performance
Industrial and Commercial devices have different internal crystals. This has a potentially significant impact on performance levels for applications requiring the lowest possible phase noise. CyberClocks Online Software displays expected performance for both options.
When changing the output frequency, the frequency transition is not guaranteed to be smooth. There can be frequency excursions beyond the start frequency and the new frequency. Glitches and runt pulses are possible, and time must be allowed for the PLL to relock.
Phase Noise Versus Jitter Performance
In most cases, the device configuration for optimal phase noise performance is different from the device configuration for optimal cycle to cycle or period jitter. CyberClocks Online Software includes algorithms to optimize performance for either parameter. Table 3. Device Programming Variables Variable Output Frequency 0 (Power on default) Output Frequency 1 Output Frequency 2 Output Frequency 3 Optimization (phase noise or jitter) Temperature range (Commercial or Industrial)
Programming Description
The CY2XF33 is a programmable device. Before being used in an application, it must be programmed with the output frequencies and other variables described in a later section. Two different device types are available, each with its own programming flow. They are described in the following sections.
Field Programmable CY2XF33F
Field programmable devices are shipped unprogrammed and must be programmed before being installed on a printed circuit board (PCB). Customers use CyberClocksTM Online Software to specify the device configuration and generate a JEDEC (extension .jed) programming file. Programming of samples and prototype quantities is available using a Cypress programmer. Third party vendors manufacture programmers for small to large volume applications. Cypress's value added distribution partners also provide programming services. Field programmable devices are designated with an "F" in the part number. They are intended for quick prototyping and inventory reduction. The CY2XF33 is one time programmable (OTP). The software is located at www.cyberclocksonline.com.
Factory Configured CY2XF33
For customers wanting ready-to-use devices, the CY2XF33 is available with no field programming required. All requests are submitted to the local Cypress Field Application Engineer (FAE) or sales representative. After the request is processed, the user receives a new part number, samples, and data sheet with the programmed values. This part number is used for additional sample requests and production orders.
Document Number: 001-53148 Rev. *B
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PRELIMINARY
CY2XF33
Absolute Maximum Conditions
Parameter VDD VIN[1] TS TJ ESDHBM JA[2] Supply Voltage Input Voltage, DC Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) Thermal Resistance, Junction to Ambient JEDEC STD 22-A114-B 0 m/s airflow Relative to VSS Non operating Description Condition Min -0.5 -0.5 -55 -40 2000 64 Max 4.4 VDD+0.5 135 135 - Unit V V C C V C/W
Operating Conditions
Parameter VDD TPU TA 3.3V Supply Voltage Range 2.5V Supply Voltage Range Power Up Time for VDD to Reach Minimum Specified Voltage (Power Ramp is Monotonic) Ambient Temperature (Commercial) Ambient Temperature (Industrial) Description Min 3.135 2.375 0.05 0 -40 Typ 3.3 2.5 - - - Max 3.465 2.625 500 70 85 Unit V V ms C C
DC Electrical Characteristics
Parameter IDD[3] Description Operating Supply Current Condition VDD = 3.465V, CLK = 150 MHz, output terminated VDD = 2.625V, CLK = 150 MHz, output terminated VOD VOD VOS VOS VIH VIL IIH0 IIH1 IIL0 IIL1 CIN0[4] CIN1[4] LVDS Differential Output Voltage Change in VOD between Complementary Output States LVDS Offset Output Voltage Change in VOS between Complementary Output States Input High Voltage Input Low Voltage Input High Current, FS0 pin Input High Current, FS1 pin Input Low Current, FS0 pin Input Low Current, FS1 pin Input Capacitance, FS0 pin Input Capacitance, FS1 pin Input = VDD Input = VDD Input = VSS Input = VSS VDD = 3.3V or 2.5V, defined in Figure 3 as terminated in Figure 2 VDD = 3.3V or 2.5V, defined in Figure 3 as terminated in Figure 2 VDD = 3.3V or 2.5V, defined in Figure 4 as terminated in Figure 2 VDD = 3.3V or 2.5V, RTERM = 100 between CLK and CLK# Min - - 247 - 1.125 - 0.7*VDD - - - -50 -20 - - Typ - - - - - - - - - - - - 15 4 Max 120 115 454 50 1.375 50 - 0.3*VDD 115 10 - - - - Unit mA mA mV mV V mV V V A A A A pF pF
Notes 1. The voltage on any input or IO pin cannot exceed the power pin during power up. 2. Simulated. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model. 3. IDD includes ~4 mA of current that is dissipated externally in the output termination resistors. 4. Not 100% tested, guaranteed by design and characterization.
Document Number: 001-53148 Rev. *B
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PRELIMINARY
CY2XF33
AC Electrical Characteristics[4]
Parameter FOUT FSC FSI AG TDC TR, TF TLOCK TLFS TJitter() Description Output Frequency[6] Frequency Stability, commercial devices[5] Frequency Stability, industrial devices[5] Aging, 10 years Output Duty Cycle Output Rise and Fall Time Startup Time Re-lock Time RMS Phase Jitter (Random) F <= 450 MHz, measured at zero crossing F > 450 MHz, measured at zero crossing 20% and 80% of full output swing Time for CLK to reach valid frequency measured from the time VDD = VDD(min) Time for CLK to reach valid frequency from FS0 or FS1 pin change fOUT = 106.25 MHz (12 kHz-20 MHz) TA = 0C to 70C TA = -40 to 85C Condition Min 50 - - - 45 40 - - - - Typ - - - - 50 50 0.35 - - 1 Max 690 35 55 15 55 60 1.0 5 1 - Unit MHz ppm ppm ppm % % ns ms ms ps
Termination Circuits
Figure 2. LVDS Termination
CLK 100 CLK#
Notes 5. Frequency stability is the maximum variation in frequency from F0. It includes initial accuracy, plus variation from temperature and supply voltage. 6. This parameter is specified in CyberClocks Online software.
Document Number: 001-53148 Rev. *B
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PRELIMINARY
CY2XF33
Switching Waveforms
Figure 3. Output Voltage Swing
CLK# VOD1 CLK VOD = VOD1 - VOD2
Figure 4. Output Offset Voltage
CLK
VOD2
50 50
CLK#
V OS
Figure 5. Output Duty Cycle Timing
CLK TDC = CLK# TPW TPERIOD TPW TPERIOD
Figure 6. Output Rise and Fall Time
CLK#
20% TR
80%
80% 20% TF
CLK
Figure 7. RMS Phase Jitter
Phase noise
Noise Power Phase noise mark
Offset Frequency f1 RMS Jitter = f2 Area Under the Masked Phase Noise Plot
Document Number: 001-53148 Rev. *B
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PRELIMINARY
CY2XF33
Ordering Information
Part Number[7] Pb-Free CY2XF33FLXCT CY2XF33FLXIT CY2XF33LXCXXXT CY2XF33LXIxxxT Field Programmable Field Programmable Factory Configured Factory Configured 6-Pin Ceramic LCC SMD - Tape and Reel 6-Pin Ceramic LCC SMD - Tape and Reel 6-Pin Ceramic LCC SMD - Tape and Reel 6-Pin Ceramic LCC SMD - Tape and Reel Commercial, 0 to 70C Industrial, -40 to 85C Commercial, 0 to 70C Industrial, -40 to 85C Configuration Package Description Product Flow
Package Drawings and Dimensions
Figure 8. 6-Pin 3.2x5.0 mm Ceramic LCC LZ06A
0.50
SIDE VIEW
1.30 Max
2.54 TYP. 0.64 TYP.
0.10 R REF. TYP. TYP. 0.20 R REF.
4 5 6
5.0
0.32 R INDEX
7
10
TYP.
9 8 3 2 1
TOP VIEW BOTTOM VIEW
Dimensions in mm General Tolerance: 0.15MM Kyocera dwg ref KD-VA6432-A Package Weight ~ 0.12 grams
001-10044-**
.
Note 7. "xxx" is a factory assigned code that identifies the programming option.
Document Number: 001-53148 Rev. *B
0.10 REF.
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0.45 REF.
1.27
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3.2
1.2 TYP.
PRELIMINARY
CY2XF33
Document History Page
Document Title: CY2XF33 High Performance LVDS Oscillator with Frequency Margining - Pin Control Document Number: 001-53148 REV. ** *A *B ECN NO. 2704379 2734005 2764787 Orig. of Change WWZ KVM Submission Date 07/09/2009 Post to external web 09/18/2009 Change VOD limits from 250/450 mV to 247/454 mV Add max limit for TR, TF: 1.0 ns Change TLOCK max from 10 ms to 5 ms Change TLFS max from 10 ms to 1 ms Description of Change
KVM/PYRS 05/11/2009 New data sheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-53148 Rev. *B
Revised September 18, 2009
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CyberClocks is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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